lutet.industries
Researching intelligent hardware architecture & co-design for the AI age.
About Me
I am a first-year PhD student in Electrical and Computer Engineering (ECE) at the University of Illinois Urbana-Champaign. I am driven by a passion for designing and optimizing hardware accelerators and compiler tools for modern workloads.
My current research focuses on compiler construction, hardware-software co-design, and intermediate representations (IR) for AI accelerators. I build systems that bridge the gap between high-level programming models (like PyTorch/NumPy) and physical execution units using LLVM/MLIR, Vitis HLS, Pallas/Mosaic, and custom hardware generation backends.
Experience
Writing & Ideas
Exploring intermediate representations and specialized target hardware in PhD studies at UIUC.
Projects
npupy_xdna
A transparent NumPy backend offloading array operations to AMD Ryzen AI NPU cores (XDNA2). Implements "spatial template" kernels for cubic and elementwise workloads with an automated offload cost classifier and compiler passes via MLIR-AIE and Peano.
tiled-ip
A dynamic-programming-driven hardware compiler for tile-based INT8 accelerators. Automatically traverses and stitches 11 parameterized IP cores into complete GPT-2 transformer blocks using shape-inference and AXI4-Stream.
tileweaver
A simple automated compiler path translating GPU kernel designs from TileLang into synthesizable HLS C++ (Vitis HLS/ScaleHLS-HIDA). Translates TIR to MLIR while preserving loop-tiling, online reductions, and shared-memory mappings.
popn2
In my free time I am also a rhythm game enthusiast. This is version 2 of a custom arcade pop'n music controller. Built around an STM32F072 mainboard with individual input pins and darlington arrays for 12V LEDs, featuring custom PCBs, firmware, and chassis.
Connect
Feel free to reach out to coordinate research, share ideas, or talk architecture & co-design!